CMOS is difficult to realize in emerging semiconductor substrates, such as high mobility channels, organic, thin-film, and 2D transistors, etc., due to imbalanced electron/hole mobility ratio, Fermi-level pinning, and/or lack of doping techniques for both n- and p-types in one substrate. As a result, the use of the conventional  unipolar logic scheme, such as push-pull NMOS or PMOS logic, is often found in circuits based on these substrates, although at the cost of very high stand-by power.

Taking advantage of a dual-rail logic style, my recent research has demonstrated near-zero stand-by power using only NMOS or PMOS transistors. The circuits using NMOS to pull up voltage levels (or PMOS to pull down) suffer the loss of Vth. Therefore, I have invented a bootstrapping circuit block, as shown below, to recover the voltage levels.

Vth loss  in series-connected AND gates in unipolar logic with and without the bootstrapping circuit block

Basic circuit block of the invented unipolar logic, and the demo chip using .5μm silicon process

The preliminary experimental results on silicon demo chips exhibit a full swing of output voltages, as well as CMOS-level stand-by power consumption.

The 20th-stage output of 22 AND gates connected in series on a silicon demo chip (MOSIS 0.5 μm) based on NMOS-only unipolar circuit, showing correct logic output

An 8-bit Full-adder based only on NMOS is functional and has CMOS-level stand-by power

 

Input and Output Waveforms from All-NMOS 8-bit Full Adder

 

All NMOS 8-bit Full-Adder Power Consumption

Note: 1. The CLK frequency is limited by non-ideal testing environment and parasitics from contact pads. Post-simulation shows a delay of 4 ns for each stage of full-adder with the 0.5um process. 2. CMOS I/O buffer is used to provide the initial complementary input and to drive the large capacitance from contact pads and testing equipment. Nonetheless, multi-stage NMOS circuits would not output correct logic values without the invented bootstrapping module, due to accumulated Vth loss.

 

In collaboration with Prof. F. Xia at Yale University, we are exploring the use of the unipolar logic circuit on MoS2 and Phosphene (Black Phosphorus), which could yield very low power consumption compared to prior arts.